[PDF] PIO 8255 (cont.) - NPTEL M Krishna kumar MAM/M3/LU9e/V1/2004 9. Block Diagram of 8255 (Architecture) ( cont.) • It has a 40 pins of 4 groups. 1. Data bus buffer 2. Read Write control logic 3. Group A and Group B controls 4. Port A, B and C • Data bus buffer: This is a tristate bidirectional buffer used to [PDF] Lecture -49 INTEL 8255: (Programmable Peripheral Interface) The 8255 A is contained in a 40 -pin package, whose pin out is shown in fig.9.1. Fig.9.1 Pin Configuration of Intel 8225 PPI The block diagram is shown in fig.9.2. Functional Description: This support chip is a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. Intel 8255 - Wikipedia The 8255 has 24 input/output pins. These are divided into three 8-bit ports (A, B, C). Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and B.