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IC 74LS138 LOGIC DIAGRAM

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SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER
The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex-pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter.
74LS138 Decoder Pinout, Features, Circuit & Datasheet
74LS138 Decoder IC. 74LS138 Decoder Pinout [Click the image to enlarge it] 74LS138 is a member from ‘74xx’family of TTL logic gates. 74LS138 is a sixteen pin device as shown in pin diagram and we will describe the function of each pin below. Pin. Name. Description. 1. A. Address input pin. 2. B.
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